In semiconductor technology, the most advanced technologies with the highest integration densities are used in particular for fabricating so-called DRAM memories (dynamic random access memory). With an increasing packing density or integration density, however, the following difficulties result for example in DRAM semiconductor memories:
In order to control a short-channel behavior (roll-off) of a selection transistor in a DRAM semiconductor memory cell, from technology generation to technology generation an associated well doping or a channel implant is increased. However, this results in a greater body effect, which in turn impairs writing behavior. The body effect is manifested in an increase in the threshold voltage of the field-effect transistor as source-body voltage increases. The term “body” hereinafter denotes in particular the semiconductor substrate situated directly in the vicinity of the transistor or of the source/drain regions and of the channel region.
During a writing operation in a DRAM memory cell with a trench capacitor (for example writing a logic “1”), the potential of a source/drain region which is connected to the trench capacitor, for example, increases with increasing charging of the corresponding trench capacitor capacitance. Given a fixed body potential, this means an increase in the voltage between the source/drain region and the body, as a result of which the transistor, depending on a charging state of the trench capacitor, increases its threshold voltage on account of the body effect. This phenomenon is generally referred to as “source follower mode”.
As a direct consequence of the increased threshold voltage, the field-effect transistor then also supplies a lower current given an otherwise identical voltage difference between a further source/drain region or a bit line and the capacitance of the trench capacitor. Consequently, the complete charging of the trench capacitor takes correspondingly longer, for which reason this body effect correspondingly limits the writing performance for example in a DRAM memory cell.
Furthermore, as the integration density increases, it becomes more and more difficult to ensure a contact connection of the local well regions, i.e. well regions relative to the selection transistor. In particular on account of depletion around the trench capacitor regions, it is difficult, in particular in the case of a high packing density, to ensure a low-impedance or highly conductive current path from the well contacts to the selection transistors without potential barriers. This is true particularly since as the well doping increases, the associated field strengths at connection regions with respect to the trench capacitor increase correspondingly.
FIG. 1 shows a simplified plan view of a conventional DRAM memory cell arrangement, where STI designates shallow trench isolations which are formed in strip-type fashion and form a multiplicity of strip-type active regions AA in a semiconductor substrate. In the active regions AA, respective first and second source/drain regions S/D with a channel region lying in between are formed to produce a field-effect transistor structure. To realize a control layer CG above the channel region, strip-type word lines WL are formed essentially perpendicular to the strip-type active regions AA, the word lines enabling the field-effect transistor structure to be driven. DTC denotes a trench capacitor (Deep Trench Capacitor) which is conductively connected to one of the source/drain regions, the further source/drain region S/D being connected to a bit line (not illustrated). Furthermore, a minimum feature size that can be fabricated lithographically is represented by F in FIG. 1.
FIG. 3 shows a simplified perspective view of the memory cell arrangement in accordance with FIG. 1 along a section I-I, identical reference symbols designating identical or corresponding elements and layers and a repeated description being dispensed with below.
In accordance with FIG. 3, a semiconductor memory cell accordingly comprises a trench capacitor DTC (deep trench capacitor) which is connected via an electrically conductive buried connection plate BP (buried plate) to further trench capacitors or the external electrodes thereof (not illustrated) in the memory array. The lower part of the trench capacitor DTC with its internal and external electrodes is not illustrated in FIG. 3.
The upper region of the trench capacitor DTC as illustrated in FIG. 3 has a trench capacitor connection layer 8 comprising, for example, polycrystalline, highly-doped semiconductor material and in particular polysilicon. For the insulation of the trench capacitor connection layer 8, the upper part of the trench capacitor DTC has a collar insulation layer 7 comprising silicon dioxide, for example. In order to connect the trench capacitor connection layer 8 to a first source/drain region S/D, by way of example, a buried layer BS (buried strap) is formed below the first source/drain region S/D. Like the first source/drain region S/D, the buried layer BS preferably constitutes a highly-doped semiconductor region of a first conduction type n, which is formed in the semi-conductor substrate of the second conduction type p, opposite to the first conduction type n. A top insulating layer 9, preferably comprising silicon dioxide, is formed in order to insulate the trench capacitor connection layer 8 from a word line WL formed at the substrate surface or the passive control layer region PCG (passive control gate) of the word line.
Furthermore, at the surface of the semiconductor substrate, a second source/drain region once again of the first conduction type n is formed in the semiconductor substrate 1, thereby defining a channel region of the field-effect transistor structure. At the surface of the channel region or of the semiconductor substrate 1, a gate insulation layer 2 is formed at least between these first and second source/drain regions S/D, at the surface of which gate insulation layer a control layer 3 (CG, control gate) as part of the word line WL formed in strip-type fashion undertakes the driving of the field-effect transistor structure. Via a bit line contact BLK, which makes contact with the second source/drain region S/D of the field-effect transistor structure, the region is connected to a bit line BL lying essentially above the word lines WL and parallel to the active regions AA formed in strip-type fashion.
For the connection of a well region (not explicitly illustrated) in the semiconductor substrate 1, a well connection doping region WA is usually provided at some distance from the field-effect transistor structure. In accordance with FIG. 3, the well connection doping region WA has a second conduction type p opposite to the first conduction type n, and usually serves for dissipating or depleting the charge carriers L that occur in the body or semiconductor substrate 1 present directly at the field-effect transistor structure.
FIG. 4 shows a simplified equivalent circuit diagram of the semiconductor memory cell in accordance with FIG. 3, identical reference symbols designating identical or corresponding elements and regions and a repeated description being dispensed with below.
In particular, the resistor R, which essentially results from an electrical conductivity of the well region or of the semiconductor substrate 1 with respect to the well connection doping region WA, increases as the integration density increases, which leads to an impairment of the function on account of the body effect described above.
In particular in DRAM semiconductor memory cells with associated trench capacitors, this problem is intensified by the fact that the trench capacitors DTC arranged in an array in accordance with FIG. 1 move ever closer together and, consequently, the clearance between the trench capacitors for dissipating the charge carriers L becomes more and more constricted. Moreover, DRAM semiconductor memory cells also do not afford the possibility of dissipating the charge carriers L via the deeper regions of the semiconductor substrate 1, since, by virtue of the buried connection plate BP for connecting the counterelectrodes of the trench capacitors DTC, an insulating layer is built up in this region.
However, an insufficient or high-impedance well connection of the body or of the semiconductor substrate in direct proximity to the field-effect transistor structure leads sooner or later to its charging and consequently, on account of the body effect, to a reduction of the effective threshold voltage and thus to increased leakage currents. In particular in the case of the DRAM semiconductor memory cell illustrated in FIG. 3, the retention time is thus impaired.